1. Field of the Invention
The present invention relates to a substrate, a semiconductor device using the same, a method for inspecting semiconductor device, and a method for manufacturing semiconductor device, and in particular to terminal arrangement on a substrate.
2. Description of the Related Art
With a demand for ever-shrinking electronic components, it is necessary to mount a large number of integrated circuit chips and circuit components on a semiconductor device mounting a semiconductor integrated circuit and circuit components. There is a growing demand for efficient use of a wiring space and a component mounting space.
There is proposed for example a laminated semiconductor device that has improved the conforming product rate with reduced mounting area per function or memory capacity (Patent Reference 1).
On this semiconductor device, a semiconductor chip is mounted face down on the main surface of a first substrate including a bonding pad arranged along the edge of the main surface of the substrate so as to expose the first bonding pad. A test is conducted using the first bonding pad to determine whether the semiconductor device is non-defective. Further, a second substrate mounting a second semiconductor chip having a similarly formed second bonding pad is mounted on the first substrate so as to expose the first bonding pad. The first and second semiconductor chips are connected to the outside by using the first and second bonding pads.
As such a semiconductor device becomes highly integrated, the number of pins goes on rising increasingly. These first and second bonding pads are not sufficient for connection. Surface mounting has been proposed using a so-called solder ball whereby substrates are interconnected via a surface contact.
For example, as shown in FIG. 11, a so-called Package on Package (PoP) has been proposed that is formed by laminating an SoC 1010 formed by horizontal mounting on a mounting substrate and a memory device 1020 as shown in FIG. 12.
Such a laminated semiconductor device reduces the mounting area as the signal wiring length. This accordingly reduces the signal wiring capacity and possible noise.
In recent years, a system design called System on Chip (SoC) has been in widespread use that integrates complicated functional macros into a single LSI. Here, the “functional macro” is a concept mainly used in the functional design stage of LSI. The functional macro refers to a single cell (block) as aggregation of circuits to implement a predetermined function and is registered in a library in the form of an IP (design resource). To form a laminated semiconductor device using such a high-integration LSI, in particular, interconnection between the first semiconductor chip mounted on the first substrate and the second semiconductor chip mounted on the second substrate is required although there arises a problem that interconnection via the first or second substrate results in failure to measure signals.
In particular, a system on chop using a high-frequency LSI used in a frequency band over 100 MHz is intended for high-speed transmission so that waveform rounding is strictly unacceptable. A delay attributable the wiring length on a substrate or wiring length to a test circuit as well as attenuation or problem with matching caused by a connection terminal such as an electrode pad are serious. Measures have been taken so that the wiring length will be minimized and the wiring capacity will be reduced. Under these circumstances, a downsized and lower-profile substrate and reduction of the number of pins and the number of conductor layers present major problems.
There are many cases where it is necessary to mount a filter component or a bypass capacitor. In case such an external component is mounted on a mounting substrate, a wiring resistance caused by the length of wiring is serious.
In this way, with a substrate that mounts semiconductor integrated circuit chips in a laminated layer structure, routing of wiring must be minimized and the impedance caused by the wiring itself must be reduced.
Each of the functional macros has a separate circuit scale and operation as well as the number of test patters required for testing. The result is a heavy load on an LSI tester. It is an important challenge to efficiently conduct the test of each functional macro.
In this way, it is one of the important challenges to efficiently conduct the test of each functional macro. With the related art laminated semiconductor device shown in FIG. 12, the second semiconductor chip is connected to the outside via the second and first substrates. This may trigger a drop in the efficiency of the test of the entire LSI including the other functional macros.    Patent Reference 1: JP-A-2005-302871